The present invention relates generally to a data processing system and more particularly to a processing system that includes power management.
A processing system includes a plurality of pipeline stages. The pipeline stages of a processing system typically comprise a fetch (F) stage, a decode (D) stage, an execute (E) stage, a memory (M) stage, and a write back (W) stage. The processing system typically includes a general purpose processor. The general purpose processor includes a core processor and an instruction cache, data cache, and writeback device which are coupled to a bus interface unit.
Typically a program run on a processing system will be executed in a manner which accommodates overall speed and power. That is, if a program""s fastest portion needs to run optimally at a certain speed, and this is critical to the operation of the program, then the entire program runs at this speed. This may consume excess power because some portions of the program may not require this speed of processing. On the other hand, if the program is optimized to run at some intermediate rate, then the program""s performance critical portions may not execute efficiently.
Oftentimes, processors have modes for power management, such as the system management mode (SMM) of the Pentium(copyright) based processors. However, to provide for these special modes requires that the program be written to recognize these modes. Oftentimes this is not desirable or feasible in low cost processing environments.
Accordingly, what is needed is a system and method for efficiently managing the power in the processing system. The system and method must be efficient, easy to implement and cost effective. The present invention addresses such a need.
A method and system for controlling a program in a processor system is disclosed. The processor system includes processor, a normal memory and a fast memory. The method and system comprises partitioning the program into a performance critical portion and a non-critical portion; and storing the performance critical portion of the program into the fast memory. The method and system further includes storing the non-critical portion in the normal memory, and causing the processor to execute the performance critical portion and non-critical portions at the appropriate time. Accordingly, through the use of the present invention power is conserved in the processing system when executing a program.